A 0.82V supply and 23.4 ppm/0C current mirror assisted bandgap reference

Traditional BGR circuits require a 1.05V supply due to the VBE of the BJT. Deep submicron CMOS technologies are limiting the supply voltage to less than 940mV. Hence there is a strong motivation to design them at lower supply voltages. The supply voltage limitation in conventional BGR is described qualitatively in this paper. Further, a current mirror-assisted technique has been proposed to enable BGR operational at 0.82V supply. A prototype was developed in 65nm TSMC CMOS technology and post-layout simulation results were performed. A self-bias opamp has been exploited to minimize the systematic offset. Proposed BGR targeted at 450mV works from 0.82-1.05V supply without having any degradation in the performance while keeping the integrated noise of 15.2µV and accuracy of 23.4ppm/0C. Further, the circuit consumes 21µW of power and occupies 73*32µm2 silicon area

A novel current reference in 45nm cmos technology

In this paper a novel CMOS temperature and supply voltage independent current reference has been proposed. This design is based on the subtraction of two scaled version PTAT (proportional to absolute temperature) currents to provide a temperature independent current reference. The design was simulated with Spectre, and implemented in 45nm CMOS technology. Simulation results shows that the proposed current reference achieves temperature coefficient of 22ppm/0C against temperature variation of -400C –1200C and line sensitivity of 337ppm/V against supply variation of 0.6–1.8V, while consuming 135uW from 1.8V supply and occupying 5184um

A 261mV bandgap reference based on beta multiplier with 64ppm

In this paper, a low voltage bandgap reference circuit has been proposed. The introduction of a modified beta multiplier bias circuit decreased the mismatch caused by the PMOS transistors opamp contribution. By shifting the fixed resistors to the NMOSs drain side, the beta multiplier bias was able to minimise threshold mismatch between the two NMOS transistors. A 200-point MC simulation showed 0.9mV standard deviation, with a 0.34% accuracy. The simulated temperature coefficient was 64ppm/0C. The proposed circuit consumed 5.04µW of power from a 0.45V power supply voltage. A prototype was implemented in 65nm CMOS technology occupying a 2888µm2 silicon area, with the nominal value of the reference at 261mV

A Microwatt low voltage bandgap reference for bio-medical applications

In this paper a microwatt low voltage bandgap reference suitable for the bio-medical application. The Present technique relies on the principle of generating CTAT and PTAT without using any (Bipolar Junction Transistor) BJT and adding them with a proper scaling factor for minimal temperature sensitive reference voltage. Beta multiplier reference circuit has been explored to generate CTAT and PTAT. Implemented in 45nm CMOS technology and simulated with Spectre. Simulation results shows that the proposed reference circuit exhibits 1.2% variation at nominal 745mV output voltage. The circuit consumes 16uW from 0.8V supply and occupying 0.004875mm2 silicon area

A high performance skin impedance measurement circuit for biomedical applications

This paper describes a high-performance impedance measurement circuit for the application of skin impedance measurement in the early detection of skin cancer. A CMRR improvement technique has been adopted for OTAs to reduce the impact of high frequency common mode interference. A modified 3-OTA IA has been proposed to help with the impedance measurement. Such systems offer a quick, non-invasive and painless procedure, thus having considerable advantages over the currently used approach, which is based upon the testing of a biopsy sample. The sensor has been implemented in 65nm CMOS technology and post layout simulations confirms the theoretical claims we made and sensor exhibits sensitivity. Circuit consumes 45uW from 1.5V power supply. The circuit occupies 0.01954mm2 silicon area

A low noise amplifier suitable for biomedical recording analog front-end in 65nm CMOS technology

This paper presents a fully integrated Front-end, low noise amplifier, dedicated to the processing of various types of bio-medical signals, such as Electrocardiogram (ECG), Electroencephalography (EEG), Axon Action Potential (AAP). A novel noise reduction technique, for an operational transconductance amplifier (OTA), has been proposed. This adds a current steering branch parallel to the differential pair, with a view to reducing the noise contribution by the cascode current sources. Hence, this reduces the overall input referred noise of the Low Noise Amplifier (LNA), without adding any additional power. The proposed technique implemented in 65nm CMOS technology achieves 30dB closed loop voltage gain, 0.05Hz lower cut-off frequency and 100MHz 3-dB bandwidth. It operates at 1.2V power supply and draws 1µA static current. The prototype described in this paper occupies 3300µm2silicon area

A Novel Sub-1V Bandgap Reference with 17.1 ppm/0C Temperature coefficient in 28nm CMOS

Traditional Banba bandgap is very popular in deep sub-micron CMOS technologies because of its sub 1V output nature. But unfortunately, it won’t provide PTAT nature current and has several operating points, unlike two in the voltage mode BGR. This work analyzes the Banba circuit in a detailed way so that it’s easy to demonstrate multiple stable operating and lists some of its other shortfalls. This paper presents a novel sub-1V bandgap architecture, which can provide PTAT current and sub-1V output without having multiple operating points. A modified self-bias opamp has been proposed to minimize the systematic offset and its temperature drift. A prototype was developed in 28nm TSMC CMOS technology and post-layout simulation results were performed. Proposed  BGR targeted at 500mV works from 1V supply without having any degradation in the performance while keeping the integrated noise of 18.2µV and accuracy of 17.1ppm/0C, while the traditional Banba was resulting 23.4ppm/0C. Further, the circuit consumes  29.8µW of power and occupies 71*39µm2silicon area